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MT46V32M16P-5B:J TR IC DRAM 512MBIT PARALLEL 66TSOP Micron Technology Inc.

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MT46V32M16P-5B:J TR IC DRAM 512MBIT PARALLEL 66TSOP Micron Technology Inc.

Name: MT46V32M16P5BJ TR IC DRAM 512MBIT PARALLEL 66TSOP Micron Technology Inc
Brand: Micron Technology Inc.
Price: 1 USD

Brand Name : Micron Technology Inc.

Model Number : MT46V32M16P-5B:J TR

MOQ : 1

Price : Based on current price

Payment Terms : T/T

Supply Ability : In stock

Delivery Time : 3-5 work days

Packaging Details : anti-static bag & cardboard box

Memory Type : Volatile

Memory Format : DRAM

Technology : SDRAM - DDR

Memory Size : 512Mbit

Memory Organization : 32M x 16

Memory Interface : Parallel

Clock Frequency : 200 MHz

Write Cycle Time - Word, Page : 15ns

Access Time : 700 ps

Voltage - Supply : 2.5V ~ 2.7V

Operating Temperature : 0°C ~ 70°C (TA)

Mounting Type : Surface Mount

Package / Case : 66-TSSOP (0.400", 10.16mm Width)

Supplier Device Package : 66-TSOP

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Product Details

Functional Description

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.

Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle(Commercial and industrial)
– 16ms, 8192-cycle (Automotive)
• Self refresh (not available on AT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)

Specifications

Attribute	Attribute Value
Manufacturer	Micron Technology Inc.
Product Category	Memory ICs
Series	-
Packaging	Tape & Reel (TR) Alternate Packaging
Package-Case	66-TSSOP (0.400", 10.16mm Width)
Operating-Temperature	0°C ~ 70°C (TA)
Interface	Parallel
Voltage-Supply	2.5 V ~ 2.7 V
Supplier-Device-Package	66-TSOP
Memory Capacity	512M (32M x 16)
Memory-Type	DDR SDRAM
Speed	5ns
Format-Memory	RAM

Descriptions

SDRAM - DDR Memory IC 512Mb (32M x 16) Parallel 200MHz 700ps 66-TSOP

DRAM Chip DDR SDRAM 512Mbit 32Mx16 2.6V 66-Pin TSOP T/R

China MT46V32M16P-5B:J TR IC DRAM 512MBIT PARALLEL 66TSOP Micron Technology Inc. wholesale

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